The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Sep. 21, 2012
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Chih Chien, Hsinchu, TW;

Ming-Hsiu Lee, Hsinchu, TW;

Feng-Ming Lee, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/5614 (2013.01); G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); G11C 2213/51 (2013.01); G11C 2213/71 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1266 (2013.01); H01L 45/146 (2013.01); H01L 27/2463 (2013.01);
Abstract

A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. A resistive memory array including an array of the above resistive memory units, word lines and bit lines is also described, wherein the word (bit) lines are coupled to the first (second) memory layers.


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