The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Dec. 07, 2012
Applicant:

Sandisk Technologies, Inc., Plano, TX (US);

Inventors:

Vinod Purayath, Santa Clara, CA (US);

George Samachisa, San Jose, CA (US);

George Matamis, Danville, CA (US);

James Kai, Santa Clara, CA (US);

Yuan Zhang, San Jose, CA (US);

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/76 (2006.01); H01L 29/788 (2006.01); H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 29/66833 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/42332 (2013.01); H01L 29/7881 (2013.01); H01L 27/11524 (2013.01); Y10S 977/943 (2013.01); Y10S 977/773 (2013.01); Y10S 977/774 (2013.01); Y10S 977/937 (2013.01); Y10S 977/938 (2013.01);
Abstract

A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.


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