The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2015
Filed:
Mar. 15, 2013
Avalanche Technology Inc., Fremont, CA (US);
Kimihiro Satoh, Beaverton, OR (US);
Yiming Huai, Pleasanton, CA (US);
Jing Zhang, Los Altos, CA (US);
Dong Ha Jung, Pleasanton, CA (US);
Avalanche Technology, Inc., Fremont, CA (US);
Abstract
Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.