The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Oct. 18, 2011
Applicants:

Zvi Or-bach, San Jose, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Ze'ev Wurman, Palo Alto, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Ze'ev Wurman, Palo Alto, CA (US);

Assignee:

Monolithic 3D Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/48 (2006.01); H01L 21/84 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/108 (2006.01); H01L 29/786 (2006.01); H01L 27/11 (2006.01); H01L 27/115 (2006.01); H01L 27/118 (2006.01); H01L 27/12 (2006.01); H01L 23/544 (2006.01); H01L 21/683 (2006.01); H01L 21/66 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/0694 (2013.01); H01L 29/7841 (2013.01); H01L 29/785 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/10802 (2013.01); H01L 29/78696 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 27/1108 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11551 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 27/11578 (2013.01); H01L 27/11803 (2013.01); H01L 27/1203 (2013.01); H01L 27/1116 (2013.01); H01L 23/544 (2013.01); H01L 21/6835 (2013.01); H01L 2221/6835 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 22/22 (2013.01); H01L 45/1616 (2013.01); H01L 45/1683 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 21/76254 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.


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