The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Oct. 11, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chia-Cheng Chang, Baoshan Township, TW;
Wei-Kuan Yu, Hsinchu, TW;
Tsai-Ming Huang, Zhubei, TW;
Chin-Min Huang, Taichung, TW;
Cherng-Shyan Tsay, Toufen Township, TW;
Chien Wen Lai, Hsinchu, TW;
Hua-Tai Lin, Hsinchu, TW;
Shih-Ming Chang, Zhubei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.