The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

May. 17, 2013
Applicant:

Novellus Systems, Inc., Fremont, CA (US);

Inventors:

Chunhai Ji, Portland, OR (US);

Sirish Reddy, Hillsboro, OR (US);

Tuo Wang, Tianjin, CN;

Mandyam Sriram, Beaverton, OR (US);

Assignee:

Novellus Systems, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/033 (2006.01); H01L 21/67 (2006.01); H01J 37/32 (2006.01); H01L 21/02 (2006.01); C23C 16/04 (2006.01); C23C 16/26 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/67069 (2013.01); H01J 37/32082 (2013.01); H01L 21/02115 (2013.01); H01L 21/02274 (2013.01); H01L 21/31122 (2013.01); C23C 16/045 (2013.01); C23C 16/26 (2013.01);
Abstract

Techniques, systems, and apparatuses for performing carbon gap-fill in semiconductor wafers are provided. The techniques may include performing deposition-etching operations in a cyclic fashion to fill a gap feature with carbon. A plurality of such deposition-etching cycles may be performed, resulting in a localized build-up of carbon film on the top surface of the semiconductor wafer near the gap feature. An ashing operation may then be performed to preferentially remove the built-up material from the top surface of the semiconductor wafer. Further groups of deposition-etching cycles may then be performed, interspersed with further ashing cycles.


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