The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Jun. 27, 2012
Applicant:
Geng Shin Shen, Tainan County, TW;
Inventor:
Geng Shin Shen, Tainan County, TW;
Assignee:
Chipmos Technologies Inc., Hsinchu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4853 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/11332 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/11318 (2013.01); H01L 2224/1132 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/11452 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/03912 (2013.01); H01L 2224/05572 (2013.01);
Abstract
The present disclosure is related to a method of providing a die structure for semiconductor packaging. The method includes providing a substrate with a bonding pad; forming a patterned mask layer on the substrate; forming an opening on the mask layer; depositing a conductive layer in the opening; forming a cap layer on the conductive layer, and removing the mask layer. The cap layer forming step allows the contacting area between the cap layer and the conductive layer to be substantially equal to the top surface area of the conductive layer by reflowing solder material prior to the removal of the mask layer.