The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Jun. 22, 2012
Applicants:

Ralf Illgen, Dresden, DE;

Stefan Flachowsky, Dresden, DE;

Inventors:

Ralf Illgen, Dresden, DE;

Stefan Flachowsky, Dresden, DE;

Assignee:

GLOBALFOUNDRIES, Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/324 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/165 (2013.01); H01L 29/51 (2013.01); H01L 29/6653 (2013.01); H01L 29/66553 (2013.01); H01L 29/66628 (2013.01); H01L 29/7834 (2013.01); H01L 29/7843 (2013.01); H01L 29/78696 (2013.01);
Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) substrate. A PFET temporary gate structure and an NFET temporary gate structure are formed on the substrate. The method implants ions to form lightly doped active areas around the gate structures. A diffusionless annealing process is performed on the active areas. Further, a compressive strain region is formed around the PFET gate structure and a tensile strain region is formed around the NFET gate structure.


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