The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2015
Filed:
Feb. 17, 2012
Nicolas Daval, Lumbin, FR;
Bich-yen Nguyen, Austin, TX (US);
Cecile Aulnette, Crolles, FR;
Konstantin Bourdelle, Crolles, FR;
Nicolas Daval, Lumbin, FR;
Bich-Yen Nguyen, Austin, TX (US);
Cecile Aulnette, Crolles, FR;
Konstantin Bourdelle, Crolles, FR;
Soitec, Bernin, FR;
Abstract
The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.