The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Jul. 15, 2013
Applicants:

Weng Foong Yap, Phoenix, AZ (US);

Douglas G. Mitchell, Tempe, AZ (US);

Inventors:

Weng Foong Yap, Phoenix, AZ (US);

Douglas G. Mitchell, Tempe, AZ (US);

Assignee:

Freescale Semiconductor Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/48 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/48 (2013.01); H01L 21/56 (2013.01);
Abstract

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.


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