The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Oct. 22, 2009
Applicants:

Nathaniel C. Berliner, Albany, NY (US);

Kangguo Cheng, Albany, NY (US);

Jason E. Cummings, Albany, NY (US);

Toshiharu Furukawa, Essex Junction, VT (US);

Jed H. Rankin, Essex Junction, VT (US);

Robert R. Robison, Essex Junction, VT (US);

William R. Tonti, Essex Junction, VT (US);

Inventors:

Nathaniel C. Berliner, Albany, NY (US);

Kangguo Cheng, Albany, NY (US);

Jason E. Cummings, Albany, NY (US);

Toshiharu Furukawa, Essex Junction, VT (US);

Jed H. Rankin, Essex Junction, VT (US);

Robert R. Robison, Essex Junction, VT (US);

William R. Tonti, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7624 (2013.01); H01L 21/30625 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 2924/0002 (2013.01); Y10S 438/959 (2013.01);
Abstract

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.


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