The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Jan. 18, 2013
Applicants:

Sailesh Kumar, San Jose, CA (US);

Eric Norige, East Lansing, MI (US);

Joji Philip, San Jose, CA (US);

Mahmud Hassan, San Carlos, CA (US);

Sundari Mitra, Saratoga, CA (US);

Joseph Rowlands, San Jose, CA (US);

Inventors:

Sailesh Kumar, San Jose, CA (US);

Eric Norige, East Lansing, MI (US);

Joji Philip, San Jose, CA (US);

Mahmud Hassan, San Carlos, CA (US);

Sundari Mitra, Saratoga, CA (US);

Joseph Rowlands, San Jose, CA (US);

Assignee:

NetSpeed Systems, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01); H04L 12/801 (2013.01);
U.S. Cl.
CPC ...
H04L 47/12 (2013.01);
Abstract

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.


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