The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Mar. 25, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Luke A. Johnson, Queen Creek, AZ (US);
Adhiveeraraghavan Srikanth, Folsom, CA (US);
Wenjun Yun, Warwick, RI (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/00 (2006.01); G06F 13/12 (2006.01); H04L 25/02 (2006.01); G06F 13/10 (2006.01); G06F 3/06 (2006.01); G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
G06F 13/122 (2013.01); G06F 13/10 (2013.01); G06F 3/067 (2013.01); G06F 13/14 (2013.01); H04L 25/0274 (2013.01); H04L 25/0282 (2013.01);
Abstract
Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.