The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Feb. 24, 2014
Applicant:
Suvolta, Inc., Los Gatos, CA (US);
Inventors:
Pushkar Ranade, Los Gatos, CA (US);
Lucian Shifren, San Jose, CA (US);
Sachin R. Sonkusale, Los Gatos, CA (US);
Assignee:
SuVolta, Inc., Los Gatos, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 21/70 (2006.01); H01L 29/78 (2006.01); H01L 27/085 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 27/085 (2013.01); H01L 29/105 (2013.01); H01L 29/1083 (2013.01); H01L 29/165 (2013.01); H01L 29/66537 (2013.01); H01L 29/6659 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7848 (2013.01); H01L 29/7835 (2013.01); H01L 27/088 (2013.01);
Abstract
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10atoms/cm, or alternatively, less than one-quarter the dopant concentration of the source and the drain.