The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Apr. 17, 2012
James V. Crain, Jr., Milton, VT (US);
Mark C. H. Lamorey, Williston, VT (US);
Christopher D. Muzzy, Burlington, VT (US);
Thomas M. Shaw, Peekskill, NY (US);
David B. Stone, Jericho, VT (US);
James V. Crain, Jr., Milton, VT (US);
Mark C. H. Lamorey, Williston, VT (US);
Christopher D. Muzzy, Burlington, VT (US);
Thomas M. Shaw, Peekskill, NY (US);
David B. Stone, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.