The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Jan. 08, 2014
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Tung-Ming Chen, Kaohsiung, TW;

Yu-Chun Huang, Tainan, TW;

Shin-Chuan Huang, Tainan, TW;

Chia-Jong Liu, Pingtung County, TW;

I-Fang Huang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 29/6659 (2013.01); H01L 29/6656 (2013.01); H01L 29/6653 (2013.01); H01L 29/66628 (2013.01); H01L 21/8238 (2013.01);
Abstract

A method for fabricating a semiconductor device is described. A semiconductor substrate is provided, wherein the substrate has a first area and a second area. A first gate structure and a second gate structure are formed over the substrate in the first area and the substrate in the second area, respectively. A first spacer is framed on the sidewall of each gate structure. At least one etching process including at least one wet etching process is performed. The first spacer is removed. A second spacer is formed on the sidewall of each gate structure. A mask layer is formed in the second area. Ion implantation is formed using the mask layer, the first gate structure and the second spacer as a mask to form S/D extensions in the substrate beside the first gate structure in the first area. The mask layer is then removed.


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