The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Nov. 03, 2011
Mahaveer Sathaiya Dhanyakumar, Hsinchu, TW;
Wei-hao Wu, Hsinchu, TW;
Tsung-hsing Yu, Taipei, TW;
Chia-wen Liu, Taipei, TW;
Tzer-min Shen, Hsinchu, TW;
Ken-ichi Goto, Hsin-Chu, TW;
Zhiqiang Wu, Chubei, TW;
Mahaveer Sathaiya Dhanyakumar, Hsinchu, TW;
Wei-Hao Wu, Hsinchu, TW;
Tsung-Hsing Yu, Taipei, TW;
Chia-Wen Liu, Taipei, TW;
Tzer-Min Shen, Hsinchu, TW;
Ken-Ichi Goto, Hsin-Chu, TW;
Zhiqiang Wu, Chubei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.