The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Jul. 14, 2011
Applicants:
Ziwei Fang, Hsinchu, TW;
Ying Zhang, Hsinchu, TW;
Jeff J. Xu, Jhubei, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/306 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30617 (2013.01); H01L 21/823814 (2013.01); H01L 21/26513 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823807 (2013.01); H01L 21/3065 (2013.01); H01L 29/66545 (2013.01); H01L 29/66628 (2013.01);
Abstract
An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.