The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8999759 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 07, 2015

Filed:

May. 23, 2013
Applicant:

Unimicron Technology Corporation, Taoyuan, TW;

Inventor:

Kan-Jung Chia, Taoyuan, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/02 (2006.01); H01L 21/50 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H05K 1/18 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/50 (2013.01); H01L 23/5389 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H05K 1/185 (2013.01); H01L 23/3121 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 2224/24227 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H05K 3/0032 (2013.01); H05K 2201/0969 (2013.01); H05K 2201/09781 (2013.01); H05K 2201/10674 (2013.01); H01L 2924/01033 (2013.01);
Abstract

A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.


Find Patent Forward Citations

Loading…