The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Apr. 16, 2013
Applicants:

Global Unichip Corporation, Hsinchu, TW;

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shi-Hao Chen, Nantou County, TW;

Tsung-Ying Tsai, Hsinchu, TW;

Chao-Yen Huang, Taipei, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5068 (2013.01); G06F 2217/40 (2013.01); G06F 2217/78 (2013.01);
Abstract

Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design.


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