The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Feb. 22, 2012
Applicants:

Yimao Cai, Beijing, CN;

Zhenni Wan, Beijing, CN;

RU Huang, Beijing, CN;

Inventors:

Yimao Cai, Beijing, CN;

Zhenni Wan, Beijing, CN;

Ru Huang, Beijing, CN;

Assignee:

Peking University, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/12 (2013.01); H01L 45/04 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 27/2436 (2013.01); G11C 13/0002 (2013.01);
Abstract

The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array.


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