The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Feb. 11, 2010
Applicants:

Der-chyang Yeh, Hsin-Chu, TW;

Hsing-kuo Hsia, Jhubei, TW;

Hao-hsun Lin, Taipei, TW;

Chih-ping Chao, Hsin-Chu, TW;

Chin-hao Su, Hsin-Chu, TW;

Hsi-kuei Cheng, Jhubei, TW;

Inventors:

Der-Chyang Yeh, Hsin-Chu, TW;

Hsing-Kuo Hsia, Jhubei, TW;

Hao-Hsun Lin, Taipei, TW;

Chih-Ping Chao, Hsin-Chu, TW;

Chin-Hao Su, Hsin-Chu, TW;

Hsi-Kuei Cheng, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 21/8249 (2006.01); H01L 21/285 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8249 (2013.01); H01L 21/28518 (2013.01); H01L 27/0623 (2013.01);
Abstract

A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.


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