The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Jan. 12, 2012
Applicants:

Seiji Shirai, Ibi-gun, JP;

Kenichi Shimada, Ibi-gun, JP;

Motoo Asai, Ibi-gun, JP;

Inventors:

Seiji Shirai, Ibi-gun, JP;

Kenichi Shimada, Ibi-gun, JP;

Motoo Asai, Ibi-gun, JP;

Assignee:

Ibiden Co,. Ltd., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 3/46 (2006.01); H05K 3/42 (2006.01); H05K 3/10 (2006.01); H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4661 (2013.01); H05K 3/421 (2013.01); H05K 3/108 (2013.01); H05K 3/381 (2013.01); H05K 3/382 (2013.01); H05K 3/423 (2013.01); H05K 2201/0129 (2013.01); H05K 2201/015 (2013.01); H05K 2201/0278 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09745 (2013.01);
Abstract

A multilayer printed wiring board includes a multilayered structure having conductor circuit layers and interlaminar insulative layers, the interlaminar insulative layers including an outermost interlaminar insulative layer, the conductor circuit layers including an outermost conductor circuit layer formed over the outermost interlaminar insulative, a filled-viahole formed in the outermost interlaminar insulative layer and having one or more metal plating fillings and completely closing a hole formed through the outermost interlaminar insulative layer such that the metal plating of the filled-viahole extends out of the hole and forms a substantially flat surface, and solder bumps including a first solder bump formed on the substantially flat surface of the filled-viahole and a second solder bump formed on a surface portion in the outermost conductor circuit layer. The substantially flat surface of the filled-viahole is leveled substantially at the same height as the surface portion of the outermost conductor circuit layer.


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