The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

May. 21, 2012
Applicants:

Shuo-fen Kuo, Hsinchu County, TW;

Jih-nung Lee, Hsinchu County, TW;

Sung-kuang Wu, New Taipei, TW;

Inventors:

Shuo-Fen Kuo, Hsinchu County, TW;

Jih-Nung Lee, Hsinchu County, TW;

Sung-Kuang Wu, New Taipei, TW;

Assignee:

Realtek Semiconductor Corp., Science Park, HsinChu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G11C 29/12 (2006.01); H03M 13/15 (2006.01); G11C 11/41 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); H03M 13/1545 (2013.01); G11C 29/12 (2013.01); G11C 11/41 (2013.01); G11C 2029/0405 (2013.01);
Abstract

A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit.


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