The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2015
Filed:
Dec. 23, 2009
Tsung-yung Chang, Hsin-Chu, TW;
Fatih Hamzaoglu, Portland, OR (US);
Gunjan H. Pandya, Portland, OR (US);
Siufu Chiu, San Jose, CA (US);
Kevin Zhang, Portland, OR (US);
Wei Chen, Sunnyvale, CA (US);
Tsung-Yung Chang, Hsin-Chu, TW;
Fatih Hamzaoglu, Portland, OR (US);
Gunjan H. Pandya, Portland, OR (US);
Siufu Chiu, San Jose, CA (US);
Kevin Zhang, Portland, OR (US);
Wei Chen, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.