The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Aug. 31, 2012
Applicants:

Akira Goda, Boise, ID (US);

Mark Helm, Santa Cruz, CA (US);

Pranav Kalavade, San Jose, CA (US);

Charan Srinivasan, Boise, ID (US);

Inventors:

Akira Goda, Boise, ID (US);

Mark Helm, Santa Cruz, CA (US);

Pranav Kalavade, San Jose, CA (US);

Charan Srinivasan, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.


Find Patent Forward Citations

Goda, Akira. (2015). Memory program disturb reduction (U.S. Patent No. 8982625). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8982625

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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