The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2015
Filed:
Apr. 08, 2013
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Wei Han, Beaverton, OR (US);
Zheng Chen, Allentown, PA (US);
Eric Lee, Allentown, PA (US);
Jie Qin, San Jose, CA (US);
Shankar Durgamahanthi, San Jose, CA (US);
Kanad Chakraborty, Portland, OR (US);
Dan Ratchen, Hillsboro, OR (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.