The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Jun. 11, 2010
Applicants:

Hang-ting Lue, Hsinchu, TW;

Tzu-hsuan Hsu, Jhongpu Township, TW;

Sheng-chih Lai, Taichung, TW;

Inventors:

Hang-Ting Lue, Hsinchu, TW;

Tzu-Hsuan Hsu, Jhongpu Township, TW;

Sheng-Chih Lai, Taichung, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); G11C 16/0483 (2013.01); H01L 21/28282 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66833 (2013.01); H01L 21/26513 (2013.01);
Abstract

An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.


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Lue, Hang-Ting. (2015). Nonvolatile memory array with continuous charge storage dielectric stack (U.S. Patent No. 8975687). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8975687

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