The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Jan. 16, 2013
Applicants:

Jinhee Jung, Busan, KR;

Youngdal Roh, Icheon-si, KR;

Kyounghee Park, Icheon-si, KR;

Inventors:

JinHee Jung, Busan, KR;

YoungDal Roh, Icheon-si, KR;

KyoungHee Park, Icheon-si, KR;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/768 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.


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