The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Jun. 27, 2013
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Xi-Wei Lin, Fremont, CA (US);

Victor Moroz, Saratoga, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G06F 17/50 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); G11C 11/412 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G06F 17/5072 (2013.01); H01L 21/823828 (2013.01); H01L 27/0207 (2013.01); G11C 11/412 (2013.01); G06F 17/5068 (2013.01); H01L 27/1104 (2013.01);
Abstract

Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.


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