The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Dec. 31, 2012
Applicant:

Win Semiconductors Corp., Kuei Shan Hsiang, Tao Yuan Shien, TW;

Inventors:

Shinichiro Takatani, Tao Yuan Shien, TW;

Jung-Tao Chung, Tao Yuan Shien, TW;

Chi-Wei Wang, Tao Yuan Shien, TW;

Cheng-Guan Yuan, Tao Yuan Shien, TW;

Shih-Ming Joseph Liu, Tao Yuan Shien, TW;

Assignee:

WIN Semiconductors Corp., Kuei Shan Hsiang, Tao Yuan Shien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01);
Abstract

The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resistor, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.


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