The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Aug. 10, 2012
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Subramanian S. Iyer, Mount Kisco, NY (US);
Steven J. Koester, Ossining, NY (US);
Fei Liu, Mount Kisco, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Albert M. Young, Fishkill, NY (US);
Roy R. Yu, Poughkeepsie, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Subramanian S. Iyer, Mount Kisco, NY (US);
Steven J. Koester, Ossining, NY (US);
Fei Liu, Mount Kisco, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Albert M. Young, Fishkill, NY (US);
Roy R. Yu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.