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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8962421 B1

PDFFull Text
Date of Patent:
Feb. 24, 2015

Filed:

Nov. 15, 2012

Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture

Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

Gopal Srinivasan, Castro Valley, CA (US);

Andy Wei, Queensbury, NY (US);

Dinesh Somasekhar, Portland, OR (US);

Ali Keshavarzi, Los Altos, CA (US);

Subi Kengeri, San Jose, CA (US);

Assignee:

GLOBALFOUNDRIES, Inc., Grand Cayman, KY;

Attorney:

Ingrassia Fisher & Lorenz, P.C.

Primary Examiner:

Charles Garber

Assistant Examiner:

Ron Pompey

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/20 (2006.01); H01L 49/02 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 28/20 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/785 (2013.01); H01L 29/66795 (2013.01); H01L 29/6681 (2013.01); H01L 29/78648 (2013.01); H01L 21/823821 (2013.01);
Abstract

A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.

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