The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Jul. 30, 2013
Brian A. Winstead, Austin, TX (US);
Cheong Min Hong, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Jane A. Yater, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Cheong Min Hong, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Jane A. Yater, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.