The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Nov. 25, 2013
Applicant:

Avalanche Technology Inc., Fremont, CA (US);

Inventors:

Benjamin Chen, San Jose, CA (US);

Kimihiro Satoh, Beaverton, OR (US);

Jing Zhang, Los Altos, CA (US);

Dong Ha Jung, Pleasanton, CA (US);

Assignee:

Avalanche Technology, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 43/02 (2013.01);
Abstract

The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.


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