The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Jul. 31, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wen-Chun Huang, Tainan, TW;

Ming-Hui Chih, Luzho, TW;

Chia-Ping Chiang, Taipei, TW;

Ru-Gun Liu, Zhubei, TW;

Tsai-Sheng Gau, Hsinchu, TW;

Jia-Guei Jou, New Taipei, TW;

Chih-Chung Huang, Hsinchu, TW;

Dong-Hsu Cheng, Tainan, TW;

Yung-Pei Chin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01);
Abstract

A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.


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