The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2015
Filed:
Mar. 03, 2014
Applicant:
Sandisk Technologies Inc., Plano, TX (US);
Inventors:
Deepanshu Dutta, Santa Clara, CA (US);
Chun-Hung Lai, Kamakura, JP;
Shih-Chung Lee, Yokohama, JP;
Ken Oowada, Fujisawa, JP;
Masaaki Higashitani, Cupertino, CA (US);
Assignee:
SanDisk Technologies Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/16 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01); G11C 16/16 (2013.01); G11C 16/349 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01);
Abstract
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.