The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2015
Filed:
Jan. 08, 2013
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Maciej Wojnowski, Munich, DE;
Walter Hartner, Bad Abbach, DE;
Ottmar Geitner, Pentling, DE;
Gottfried Beer, Nittendorf, DE;
Klaus Pressel, Regensburg, DE;
Mehran Pour Mousavi, Munich, DE;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/66 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01Q 1/22 (2006.01); H01Q 9/04 (2006.01); H01Q 9/16 (2006.01); H01Q 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/76885 (2013.01); H01L 21/76802 (2013.01); H01L 23/49827 (2013.01); H01Q 1/2283 (2013.01); H01Q 9/0407 (2013.01); H01Q 9/16 (2013.01); H01Q 23/00 (2013.01); H01L 2924/0002 (2013.01); H01L 23/3128 (2013.01);
Abstract
In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.