The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2015
Filed:
Jul. 29, 2008
Shih-yu Wang, Hsinchu, TW;
Chia-ling LU, Hsinchu, TW;
Yan-yu Chen, Hsinchu, TW;
Yu-lien Liu, Hsinchu, TW;
Tao-cheng LU, Hsinchu, TW;
Shih-Yu Wang, Hsinchu, TW;
Chia-Ling Lu, Hsinchu, TW;
Yan-Yu Chen, Hsinchu, TW;
Yu-Lien Liu, Hsinchu, TW;
Tao-Cheng Lu, Hsinchu, TW;
MACRONIX International Co., Ltd., Hsinchu, TW;
Abstract
An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.