The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2015
Filed:
Sep. 11, 2012
Reinhard Hess, Straubing, DE;
Katharina Umminger, Lappersdorf, DE;
Gabriel Maier, Regensburg, DE;
Markus Menath, Regensburg, DE;
Gunther Mackh, Neumarkt, DE;
Hannes Eder, Villach, AT;
Alexander Heinrich, Regensburg, DE;
Reinhard Hess, Straubing, DE;
Katharina Umminger, Lappersdorf, DE;
Gabriel Maier, Regensburg, DE;
Markus Menath, Regensburg, DE;
Gunther Mackh, Neumarkt, DE;
Hannes Eder, Villach, AT;
Alexander Heinrich, Regensburg, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.