The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Feb. 24, 2012
Applicants:

Wenliang Dai, Shanghai, CN;

Lanbing Chen, Shanghai, CN;

Guoying Feng, Shanghai, CN;

Ping Liu, Shanghai, CN;

Dennis Nagle, Peabody, MA (US);

Jilin Tan, Nashua, NH (US);

Wenjian Zhang, Shanghai, CN;

Qi Zhao, Shanghai, CN;

Zhongyong Zhou, Shanghai, CN;

Inventors:

Wenliang Dai, Shanghai, CN;

Lanbing Chen, Shanghai, CN;

Guoying Feng, Shanghai, CN;

Ping Liu, Shanghai, CN;

Dennis Nagle, Peabody, MA (US);

Jilin Tan, Nashua, NH (US);

Wenjian Zhang, Shanghai, CN;

Qi Zhao, Shanghai, CN;

ZhongYong Zhou, Shanghai, CN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/5018 (2013.01); G06F 17/5036 (2013.01); G06F 17/509 (2013.01); G06F 2217/78 (2013.01);
Abstract

The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are also within the scope of the present disclosure.


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