The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Sep. 17, 2013
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon, KR;

Inventors:

Jung Hyun Park, Hwaseong, KR;

Nam Keun Oh, Daejeon, KR;

Sang Duck Kim, Cheongju, KR;

Jong Gyu Choi, Yeongi, KR;

Young Ji Kim, Daejeon, KR;

Ji Eun Kim, Gwangmyeong, KR;

Myung Sam Kang, Hwaseong, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/332 (2006.01); H01L 21/768 (2006.01); H01L 23/13 (2006.01); H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76885 (2013.01); H01L 23/13 (2013.01); H01L 24/97 (2013.01); H01L 21/02112 (2013.01); H01L 23/3128 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/4824 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01078 (2013.01); H01L 24/48 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A method of manufacturing a ball grid array substrate includes: forming a first circuit pattern and a second circuit pattern on a first metal carrier and a second metal carrier, respectively; stacking a first insulating layer and a second insulating layer with a separable material interposed therebetween, wherein each of the first and second insulating layers has first and second surfaces opposing each other, and the first surface contacts the separable material; burying the first and second circuit patterns in the second surfaces of the first and second insulating layers, respectively; removing the first and second metal carriers; removing the separable material to separate the first and second insulating layers from each other; and forming an opening in each of the first and second insulating layers to connect the first and second surfaces with each other. The method may also be part of a process for manufacturing a semiconductor package.


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