The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Jul. 08, 2013
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chun Hsiung Tsai, Xinpu Township, TW;

Shiang-Rung Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 29/04 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/04 (2013.01); H01L 21/2022 (2013.01);
Abstract

The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.


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