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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8940638 B1

PDFFull Text
Date of Patent:
Jan. 27, 2015

Filed:

Feb. 23, 2011

Substrate wiring method and semiconductor manufacturing device

Applicants:

Satohiko Hoshino, Yamanashi, JP;

Hidefumi Matsui, Yamanashi, JP;

Masaki Narushima, Yamanashi, JP;

Inventors:

Satohiko Hoshino, Yamanashi, JP;

Hidefumi Matsui, Yamanashi, JP;

Masaki Narushima, Yamanashi, JP;

Assignees:

Tokyo Electron Limited, Tokyo, JP;

Iwatani Corporation, Osaka-shi, JP;

Attorney:

Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Cheung Lee

Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); C23C 14/04 (2006.01); C23C 14/22 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01); C23C 16/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76814 (2013.01); C23C 14/046 (2013.01); C23C 14/221 (2013.01); H01L 21/02063 (2013.01); H01L 21/28556 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/53238 (2013.01); C23C 16/0281 (2013.01); H01L 23/5222 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Find Patent Forward Citations

Hoshino, Satohiko. (2015). Substrate wiring method and semiconductor manufacturing device (U.S. Patent No. 8940638). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8940638

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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