The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2015
Filed:
Jul. 22, 2014
Cadence Design Systems, Inc., San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Systems and methods for generating Extracted Timing Models (ETM) for use in an analysis of the timing of an integrated circuit design in which common paths that contribute to Common Path Pessimism (CPP) are identified and included in the generated ETM such that a CPP removal algorithm implemented during the timing analysis will be properly adjusted to remove such pessimism. To generate an ETM, the clock latency paths will be characterized, taking into account the pins and timing arcs that are necessary for the identification and removal of common path pessimism, the timing information of the topologically crucial points of the design block will be retained in the ETM, and the non-essential and noisy information will be removed from the ETM to ensure that the ETM is robust and compact.