The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2015
Filed:
Jun. 05, 2013
Semiconductor Manufacturing International Corp., Shanghai, CN;
Fumitake Mieno, Shanghai, CN;
Youfeng He, Shanghai, CN;
Abstract
The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.