The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Jul. 09, 2012
Applicants:

Sen-hong Syue, Hsin-Chu, TW;

Chung-chun Ho, Taichung, TW;

Pu-fang Chen, Hsin-Chu, TW;

Shiang-bau Wang, Pingzchen, TW;

Inventors:

Sen-Hong Syue, Hsin-Chu, TW;

Chung-Chun Ho, Taichung, TW;

Pu-Fang Chen, Hsin-Chu, TW;

Shiang-Bau Wang, Pingzchen, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); G11B 20/18 (2006.01); H01L 29/78 (2006.01); H01L 29/68 (2006.01); G03F 1/00 (2012.01); G03F 1/36 (2012.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02337 (2013.01); H01L 21/762 (2013.01); G11B 20/1833 (2013.01); H01L 29/7833 (2013.01); H01L 29/68 (2013.01); G11B 2020/183 (2013.01); G11B 2020/1836 (2013.01); G11B 20/18 (2013.01); G03F 1/144 (2013.01); G03F 1/36 (2013.01); G03F 7/70425 (2013.01);
Abstract

A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.


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