The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Mar. 01, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ying Li, Newburgh, NY (US);

Henry K. Utomo, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 21/76832 (2013.01); H01L 21/76897 (2013.01); H01L 21/823842 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01);
Abstract

A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.


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