The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Jan. 31, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Cheng Ching, Zhubei, TW;

Shi Ning Ju, Hsinchu, TW;

Cary Chia-Chiung Lo, Taipei, TW;

Huicheng Chang, Tainan, TW;

Chun Chung Su, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/76 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01);
Abstract

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.


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