The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Jan. 28, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jeffrey B. Johnson, Essex Junction, VT (US);

Ramachandran Muralidhar, Mahopac, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Viorel C. Ontalus, Danbury, CT (US);

Kai Xiu, Pleasantville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/78 (2013.01); H01L 29/0847 (2013.01); H01L 29/66636 (2013.01); H01L 29/165 (2013.01);
Abstract

A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.


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